1. Field of the Invention
This invention relates, on the one hand, to a programmable interrupt controller intended to receive interrupt requests from a plurality of interrupt sources (peripheral elements: inputs-outputs, coprocessors, etc.) and, after hierarchization, to communicate these interrupt requests to the microprocessor via the data bus and, on the other hand, to a microprocessing interrupt system using this controller and to an interrupt control process.
2. Discussion of the Background
In a microprocessing system such as the one represented in FIG. 1, the peripheral elements perform tasks independently of the microprocessor, designated .mu.P 100, and must be able to communicate with this microprocessor in a random manner over time, i.e., according to asynchronous functioning. The peripheral element transmits an interrupt request signal that is processed by an interrupt controller, designated by "PIC" 102. The latter is a circuit that generally has eight hierarchized interrupt levels. When one or more "interrupt request" inputs from the controller is (are) activated, the controller 102 determines which request has the highest priority and consequently provides to the microprocessor 100 a specific interrupt signal of the selected interrupt request.
Interrupt controllers of the 8259 series that the INTEL Corporation company produces are described in the publication "Microprocessor and Peripheral Handbook" of INTEL, pages 3-171 to 3-195 of October 1988.
FIG. 2 is a block diagram of interrupt controller 8259A. European patents EP--0 358 330 and EP 0 426 331 describe interrupt controllers of the type of the 8259A. This 8259A interrupt controller receives on its inputs IR0 to IR7 up to eight hierarchized interrupt requests. As soon as an interrupt request appears on one of inputs IR0 to IR7, the interrupt controller stores it and addresses, by its output INT, an interrupt request to the microprocessor. The microprocessor ends the instruction in progress and generates two pulses on input/INTA of the controller. The latter then sends, on the data bus, a specific interrupt code.
The controller comprises a register of the interrupt requests that receives the eight "interrupt requests" inputs (1 bit per input IRi). This register is called "INTERRUPT REQUEST REGISTER" and is designated by IRR 100. A register of the in-service interrupts has stored the request being serviced or executed or the requests when the request in progress has been interrupted by a higher priority request. This register is called "IN-SERVICE REGISTER" and is designated by ISR 112. A functional block called "PRIORITY RESOLVER" 114 determines the priorities stored in the IRR register and sends a specific code of the priority selected into register ISR. An interrupt mask register makes it possible to inhibit or enable individually each interrupt level. It is designated by IMR ("INTERRUPT MASK REGISTER") 116.
Since bit IRRi is active, bit ISRi is activated by the "PRIORITY RESOLVER" 114 functional block on receipt of a pulse/INTA, if level i is of higher priority than the other active levels in register IRR and in register ISR and if IMRi=0. It is deactivated by an end-of-interrupt command in the interrupt routine (except Automatic End of Interrupt Mode).
An active ISR bit means that the microprocessor has acknowledged the request by a sequence INTA. Either the microprocessor is in the process of executing the associated interrupt routine, or it has begun to do it but it has been rerouted to a higher priority interrupt routine. Several bits can therefore be active simultaneously.
The block called "PRIORITY RESOLVER" 114 has an additional piece of information available, which is the level with which the lowest priority is associated. By default, this level is IR7 but it can be modified by the rotating priority mode ("Specific Rotation or Automatic Rotation"). The priorities associated with the other levels result from it by simple rotation.
Several INTEL 8259A controllers can be associated to increase the number of interrupt levels. One of the controllers becomes the master controller, the others being the slave controllers. The master controller that is connected to the microprocessor is tasked with hierarchizing the interrupts arriving at the various controllers. This solution lacks flexibility.
European patent EP--0 426 081 describes a programmable interrupt controller that can be associated with other identical controllers in the master--slave type relationship.